Metals are utilized for a variety of applications in semiconductor chips. One example of such applications includes the interconnect wiring. One means of depositing interconnect structures of some metals is electroplating on to semiconductor structures.
Recently, copper has started to replace aluminum in interconnect structures in integrated circuit chips. Replacement of aluminum with copper stems at least in part from the lower electrical resistivity of copper. As a result, utilizing copper has resulted in an improvement in IC chip performance. These advantages are described by Luther et al., Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference, 1993, p. 15; and by Edelstein, Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference, 1995, p. 301, the entire contents of both of which are hereby incorporated by reference.
One method that may be utilized to deposit copper for on-chip interconnect structures is the damascene method. U.S. Pat. No. 5,612,254, the entire contents of the disclosure of which are incorporated herein by reference, discloses a damascene process. Typically, copper is electroplated to form the structures, as described by Andricacos et al., IBM J. Res. Develop., 42, 567 (1998), the entire contents of the disclosure of which is hereby incorporated by reference. Electroplating and the damascene method provide a lower cost versatile method for deposition of copper.
Electroplated damascene technology typically starts with the deposition on a semiconductor wafer and patterning of dielectric material. Next, a barrier material may be deposited over an entire surface of the wafer including the dielectric material and any underlying portions of the semiconductor wafer exposed by the patterning. The barrier material may serve to isolate the silicon circuitry formed in and on the semiconductor wafer from the copper interconnection.
Subsequent to providing the layer of barrier material, a thin conducting layer may be deposited over the barrier material. This "seed" layer may act to carry the electrical current for the electroplating process. While the thin conducting layer may comprise any metal(s) or alloy(s), typically, the thin conducting layer is copper.
After providing a seed layer, the metal to make up the interconnection structure may be electrodeposited over the entire surface of the wafer, filling the patterns of lines and vias in the dielectric and simultaneously forming an "overburden" on the top of the dielectric. The overburden may then be removed. Typically, the removal is accomplished by chemical-mechanical polishing.
In some cases, a dual damascene technique may be utilized. A dual damascene technique is described by U.S. Pat. No. 5,814,557, the entire contents of the disclosure of which is hereby incorporated by reference. According to the dual damascene technique, two levels, a via level and a line level, may be patterned and deposited in a single step. By creating both of these levels simultaneously, a dual damascene technique may provide cost savings.